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ISL6144
P loss ( D1 ) = P loss ( D2 ) = --------------- ? V F = 20A ? 0.5V = 10W
D 1
INPUT BUS 1
0.5V@ 20A
36VDC TO 75 VDC
CIN1 C d1 10
PC
220nF
100μF
-S
-IN
High Voltage Pass and Clamp
A high voltage pass and clamping circuit prevents the high
output voltage from damaging the comparators in case of
quick drop in V IN . The comparators are running from the 5V
supply between HVREF and V IN . These devices are rated
for 5V and will be damaged if V OUT is allowed to be present
(as the output is powered from other parallel supplies), and
does not fall when V IN is falling. For example, if V IN falls to
30V, V OUT remains at 48V and the differential Voltage
between the “-” and “+” terminals of the comparator would be
18V, exceeding the rating of the devices and causing
permanent damage to the IC.
Fault Detection Block
The fault detection block has two monitoring circuits (refer to
Figure 2):
1. Gate monitoring detects when the GATE < V IN + 0.37V
2. V OUT monitoring detects when V IN - 0.41V > V OUT
These two outputs are ORed, inverted, level shifted, and
delayed using an internal filter ( t FLT )
The following failures can be detected by the fault detection
circuitry:
1. ORing FET off due to dead short in the sourcing supply,
leading to V IN < V OUT
2. Shorted terminals of the ORing FET
3. Blown fuse in the power path of the sourcing supply
4. Open Gate terminal
Application Considerations
ORing MOSFET Selection
Using an ORing MOSFET instead of an ORing diode results
in increased overall power system efficiency as losses
across the ORing elements are reduced. The use of ORing
MOSFETs becomes more important at higher current levels,
as power loss across the traditionally used ORing diode is
very high. The high power dissipation across these diodes
requires special thermal design precautions such as heat
sinks and forced airflow.
For example, in a 48V, 40A (1+1) redundant system with
current sharing, using a Schottky diode as the ORing
(auctioneering) device (see Figure 3), the forward voltage
drop is in the 0.4V to 0.7V range. Let us assume it is 0.5V,
power loss across each diode is as shown in Equation 4:
I OUT
(EQ. 4)
Total power loss across the two ORing diodes is 20W.
DC/DC
#1
+OUT1 = 48V
+IN +OUT
R pb1
+S
C cs1 SC (Note 11)
1nF Figure 14
PR
VOUT
(40A)
-OUT
+S
-S
5. H VREF UV
The FAULT pin is not latched off and the pull down will shut
off as soon as the fault is removed and the pin becomes high
impedance. Typically, an external pull-up resistor is
connected to an external voltage source (for example 5V,
3.3V) to pull the pin high, an LED can be used to indicate the
presence of a fault.
GATE
INPUT BUS 2
36VDC TO 75 VDC
C IN2 C d2
100μF 220nF
C cs2
1nF
SECONDARY
GROUND
DC/DC
#2
+OUT2 = 48V
+IN +OUT
R pb2
10
PC
SC (Note 11)
Figure 14
PR
-IN
-OUT
D 2
0.5V@ 20A
FAULT
DELAY
0.37V +-
VIN
PRIMARY GROUND
FIGURE 3. 1 + 1 REDUNDANT SYSTEM WITH DIODE ORing
120μs
LEVEL SHIFT
0.41V
+
-
VOUT
If a 5m Ω single MOSFET per feed is used, the power loss
across each MOSFET is as shown in Equation 5:
P loss ( M 1 ) = P loss ( M 2 ) = ? --------------- ? ? r DS ( ON )
? 2 ?
I OUT 2
(EQ. 5)
P loss ( M 1 ) = ( 20A ) ? 5m Ω = 2W
FIGURE 2. FAULT DETECTION BLOCK
8
2
Total power loss across the two ORing MOSFETs is 4W.
In case of failure of current sharing scheme, or failure of
DC/DC #1, the full load will be supplied by DC/DC #2. ORing
MOSFET M2 or ORing Diode D 2 will be conducting the full
FN9131.7
October 6, 2011
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